FPGA Design and Codesign

Model, implement, and verify FPGA designs

HDL Coder™ and HDL Verifier™ accelerate the development of FPGA and ASIC designs by helping you complete your work in days or weeks rather than in months. Additionally, HDL Coder integrates with FPGA design tools and IP from Xilinx® and Altera® to provide target-optimized implementations.

With HDL Coder and HDL Verifier, you can:

  • Model, simulate, and explore your algorithms in MATLAB and Simulink
  • Generate either target-independent or target-optimized HDL code
  • Program Xilinx and Altera FPGAs from MATLAB® and Simulink®
  • Verify your FPGA design against system-level specifications

You can also use HDL Coder and HDL Verifier to generate and verify target-independent Verilog or VHDL for your ASIC designs.

Free FPGA Design Information Kit

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FPGA Design Trial Software

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Siglead

Siglead

"MATLAB, Simulink, and HDL Coder are indispensable for us because we simulate, debug, and verify our design as an executable specification and then generate the initial HDL in almost no time."

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Eric Cigan

What's New

From Eric Cigan , FPGA Design and Codesign Technical Expert

MATLAB EXPO 2014
KOREA

May 15, Seoul

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